Designing and Verifying an AHB to APB Bridge: My Learning Experience

Being a Design Verification Trainee, I'm engaged in handling various projects that require the verification of complex digital systems. During my apprenticeship, I learned and lived in the field and got hands-on experience in validating semiconductor designs. Out of the projects handled so far, the project involving the AMBA (Advanced Microcontroller Bus Architecture) protocol stands special because this is the backbone of high-performance SoC (System-on-Chip) designs.

Through training, I've worked significantly with the AHB to APB bridge, a very critical component in SoC designs. Through this blog, I'm trying to gather my learning insight—how these protocols work, why they're important, and how the implementation of these protocols shapes modern electronic systems.

The SoC design, in today's modern design, requires communication between high-performance processing units and peripheral devices. AHB to APB bridge is a key role in data transfer between Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus (APB), which is a part of ARM's AMBA protocol family. This blog delves into the importance, architecture, and verification of the AHB2APB bridge and its optimization of SoC performance.

Understanding the AHB to APB Bridge

What is AHB and APB?

AHB (Advanced High-Performance Bus): It is a high-speed, high-bandwidth bus that is used for processors, memory controllers, and high-speed peripherals.

APB (Advanced Peripheral Bus): It is a simple, low-power, non-pipelined bus used for slow peripherals like UARTs, timers, and GPIOs.

Since AHB is optimized for speed and APB for low power, an AHB to APB Bridge is required to translate signals between them, ensuring proper data transfer.

Why Bridging is Necessary?

AHB is meant for high-speed transactions. It supports burst transfers, pipelining, and arbitration. Hence, it is used in CPUs, memory controllers, and high-bandwidth peripherals. APB is optimized for low-power, simple, and slow-speed peripherals like timers, UARTs, and GPIOs. Bridging these buses is necessary because:

AHB is a complex, high-speed protocol, whereas APB is non-pipelined and simpler.

It ensures data consistency and smooth communication between these two protocols.

It assists in power efficiency and simplifies the interface complexity.

AHB to APB Bridge Architecture

The AHB to APB bridge consists of three main sections:

AHB Interface (Master Side):

Handles incoming transactions from the AHB master.

Extracts address, data, and control signals.

Control Logic:

Converts AHB burst transfers into single APB transactions.

Generates appropriate APB enable, select, and write/read control.

APB Interface (Slave Side):

Sends correctly formatted transactions to APB peripherals.

Ensures that timing constraints and bus protocols are maintained.

AHB to APB Read and Write Cycle

Write Cycle:

AHB master initiates a write by sending HWRITE, HADDR, and HWDATA.

The bridge decodes the address and sends PWRITE, PADDR, and PWDATA to APB.

The APB peripheral processes the write operation and acknowledges.

Read Cycle:

AHB master requests data by sending HADDR and HWRITE = 0.

The bridge translates this request and signals PADDR to the APB slave.

The APB slave responds with PRDATA, which is returned to AHB.

Code Implementation of AHB to APB Bridge

Below is an example of SystemVerilog for write transactions:

`class ahb_to_apb_bridge;
function void ahb_to_apb_write(input logic [31:0] addr, input logic [31:0] data);
ahb_haddr = addr;
ahb_hwdata = data;
ahb_hwrite = 1;
ahb_htrans = 2'b10;
end
wait (ahb_hreadyout);
apb_pwdata = ahb_hwdata;
apb_paddr = ahb_haddr;
apb_pwrite = 1;
apb_penable = 1;
endfunction
endclass

`

This function converts an AHB write transaction into an APB-compliant write transfer by appropriately altering the control and enable signals.

Validation of AHB to APB Bridge by using UVM
Testbench consists of the following components

Driver
Activates transactions on the bridge
Monitor
Captures data transfers checking correctness in data transfer.
Scoreboard
Comparison of expected vs. actual results.
Coverage
Ensures all possible scenarios are run
Example UVM Driver Code:

`

`
`

class ahb_driver extends uvm_driver #(ahb_xtn);
task run_phase(uvm_phase phase);
vif.ahb_drv.HWRITE <= xtn.HWRITE;
vif.ahb_drv.HTRANS <= xtn.HTRANS;
vif.ahb_drv.HSIZE <= xtn.HSIZE;
vif.ahb_drv.HADDR <= xtn.HADDR;
vif.ahb_drv.HREADYin <= 1'b1;
vif.ahb_drv.HBURST <= xtn.HBURST;
@ (vif.ahb_drv)
wait (vif.ahb_drv.HREADYout)
vif.ahb_drv.HWDATA <= xtn.HWDATA
endtask
endclass`

Conclusion

This bridge is a crucial component in SoC designs and allows high-speed processors to interface with low-power peripherals seamlessly, translating AHB transactions into APB transactions and ensuring smooth data flow, proper synchronization, and power efficiency.

It details AHB2APB bridge design, ranging from architecture to implementation and verification. Working on this project not only enhanced my technical understanding but also improved my design verification skills.

Sharing the knowledge through this blog will benefit fellow engineers and students in VLSI, embedded systems, electrical engineering, and computer architecture.